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etrontech em658160 etron technology, inc. no. 6, technology rd. v, science-based industrial park, hsinchu, taiwan 30077, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc., reserves the right to make changes to its products and specifications without notice. 4m x 16 ddr synchronous dram (sdram) etron confidential (rev. 1.1 jan./2002) features ? fast clock rate: 300/285/250/200/166/143/125mhz ? differential clock ck & /ck ? bi-directional dqs ? dll enable/disable by emrs ? fully synchronous operation ? internal pipeline architecture ? four internal banks, 1m x 16-bit for each bank ? programmable mode and extended mode registers - /cas latency: 2, 2.5, 3 - burst length: 2, 4, 8 - burst type: sequential & interleaved ? individual byte write mask control ? dm write latency = 0 ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? precharge & active power down ? power supplies: v dd = 3.3v 0.3v v ddq = 2.5v 0.2v ? interface: sstl_2 i/o interface ? package: 66 pin tsop ii, 0.65mm pin pitch ordering information part number frequency package em658160ts-3.3 300mhz tsop ii em658160ts-3.5 285mhz tsop ii em658160ts-4 250mhz tsop ii em658160ts-5 200mhz tsop ii em658160ts-6 166mhz tsop ii em658160ts-7 143mhz tsop ii em658160ts-8 125mhz tsop ii overview pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /w e /cas /ras /cs nc bs0 bs1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss the em658160 sdram is a high-speed cmos double data rate synchronous dram containing 64 mbits. it is internally configured as a quad 1m x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, ck). data outputs occur at both rising edges of ck and /ck. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the em658160 provides programmable read or write burst lengths of 2, 4, 8, full page. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. in addition, em658160 features programmable dll option. by having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.
etrontech 4mx16 ddr sdram em658160 etron confidential 2 rev. 1.1 jan. 2002 block diagram refresh counter column counter address buffer a0 a11 bs0 bs1 control signal generator ldm, udm dll clock buffer command decoder column decoder sense amplifier row decoder 1mx16 cell array (bank #0) sense amplifier column decoder row decoder 1mx16 cell array (bank #3) mode register ck /ck cke /cs /ras /cas /we a10/ap dq0 h dq15 sense amplifier column decoder row decoder 1mx16 cell array (bank #1) sense amplifier column decoder row decoder 1mx16 cell array (bank #2) ldqs, udqs data strobe buffer dq buffer
etrontech 4mx16 ddr sdram em658160 etron confidential 3 rev. 1.1 jan. 2002 pin descriptions table 1. pin details of em658160 symbol type description ck, /ck input differential clock: ck, /ck are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. both ck and /ck increment the internal burst counter and controls the output registers. cke input clock enable: cke activates(high) and deactivates(low) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. bs0, bs1 input bank select: bs0 and bs1 defines to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0-a11 input address inputs: a0-a11 are sampled during the bankactivate command (row address a0-a11) and read/write command (column address a0-a7with a10 defining auto precharge). /cs input chip select: /cs enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when /cs is sampled high. /cs provides for external bank selection on systems with multiple banks. it is considered part of the command code. /ras input row address strobe: the /ras signal defines the operation commands in conjunction with the /cas and /we signals and is latched at the positive edges of ck. when /ras and /cs are asserted "low" and /cas is asserted "high," either the bankactivate command or the precharge command is selected by the /we signal. when the /we is asserted "high," the bankactivate command is selected and the bank designated by bs is turned on to the active state. when the /we is asserted "low," the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. /cas input column address strobe: the /cas signal defines the operation commands in conjunction with the /ras and /we signals and is latched at the positive edges of ck. when /ras is held "high" and /cs is asserted "low," the column access is started by asserting /cas "low." then, the read or write command is selected by asserting /we "high " or low"." /we input write enable: the /we signal defines the operation commands in conjunction with the /ras and /cas signals and is latched at the positive edges of ck. the /we input is used to select the bankactivate or precharge command and read or write command. ldqs, udqs input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0-dq7, udm masks dq8-dq15. dq0 - dq15 input / output data i/o: the dq0-dq15 input and output data are synchronized with the positive edges of ck and /ck. the i/os are byte-maskable during writes.
etrontech 4mx16 ddr sdram em658160 etron confidential 4 rev. 1.1 jan. 2002 v dd supply power supply: +3.3v 0.3v v ss supply ground v ddq supply dq power: +2.5v 0.2v. provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these pins should be left unconnected.
etrontech 4mx16 ddr sdram em658160 etron confidential 5 rev. 1.1 jan. 2002 operation mode fully synchronous operations are performed to latch the commands at the positive edges of ck. table 2 shows the truth table for the operation commands. table 2. truth table (note (1), (2) ) command state cke n-1 cke n dm bs 0,1 a 10 a 0-9,11 /cs /ras /cas /we bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) hxxvl lhll write and autoprecharge active (3) hxxvh column address (a0 ~ a7) lh l l read active (3) hxxvl lhlh read and autoprecharge active (3) hxxvh column address (a0 ~ a7) lh l h mode register set idle h x x op code l l l l extended mrs idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) hxxxxxlhhl device deselect any h xxxx x hxxx autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l hxxx x hxxx (selfrefresh) lh h h clock suspend mode entry activeh l xxx x xxxx power down mode entry any (5) h l xxx x hxxx lh h h clock suspend mode exit activel hxxx x xxxx power down mode exit any l hxxx x hxxx (powerdown) lh h h data write/output enable activehxlxxxxxxx data mask/output disable activehxhxxxxxxx note: 1. v=valid data, x=don't care, l=low level, h=high level 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by bs signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is clock suspend mode.
etrontech 4mx16 ddr sdram em658160 etron confidential 6 rev. 1.1 jan. 2002 mode register set (mrs) the mode register is divided into various fields depending on functionality. ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8. a2 a1 a0 burst length 0 0 0 reserved 001 2 010 4 011 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ? addressing mode select field (a3) the addressing mode can be one of two modes, both interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 2,4 and 8. a3 addressing mode 0 sequential 1 interleave --- addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device. the internal column address is varied by the burst length as shown in the following table. data n 01234567 column address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 2 words burst length 4 words 8 words full page (even starting address) --- addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. data n column address burst length data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0# 4 words data 2 a7 a6 a5 a4 a3 a2 a1# a0 data 3 a7 a6 a5 a4 a3 a2 a1# a0# 8 words data 4 a7 a6 a5 a4 a3 a2# a1 a0 data 5 a7 a6 a5 a4 a3 a2# a1 a0# data 6 a7 a6 a5 a4 a3 a2# a1# a0 data 7 a7 a6 a5 a4 a3 a2# a1# a0#
etrontech 4mx16 ddr sdram em658160 etron confidential 7 rev. 1.1 jan. 2002 ? cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck a6 a5 a4 cas latency 0 0 0 reserved 010 2 clocks 011 3 clocks 1 0 1 reserved 1 1 0 2.5 clocks 1 1 1 reserved (3.5 clocks) ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. a8 a7 test mode 0 0 normal mode 1 0 dll reset x 1 test mode ? ( bs0, bs1) bs1 bs0 an ~ a0 rfu 0 mrs cycle rfu 1 extended functions (emrs) extended mode register set (emrs) bs1 bs0 a11~ a1 a0 rfu 1 rfu 0 dll enable rfu 1 rfu 1 dll disable
etrontech 4mx16 ddr sdram em658160 etron confidential 8 rev. 1.1 jan. 2002 absolute maximum rating symbol item rating unit note v in , v out input, output voltage - 0.3~ v dd + 0.3 v 1 v dd , v ddq power supply voltage - 0.3~3.6 v 1 t opr operating temperature 0~70 c 1 t stg storage temperature - 55~150 c 1 t solder soldering temperature (10s) 260 c 1 p d power dissipation 1 w 1 i out short circuit output current 50 ma 1 recommended d.c. operating conditions (ta = 0 ~ 70 c) parameter symbol min. max. unit note power supply voltage v dd 3.0 3.6 v power supply voltage (for i/o buffer) v ddq 2.3 2.7 v input reference voltage v ref 1.15 1.35 v termination voltage v tt v ref - 0.04 v ref + 0.04 v input high voltage (dc) v ih (dc) v ref + 0.18 v ddq + 0.3 v input low voltage (dc) v il (dc) -0.3 v ref ? 0.18 v input voltage level, clk and clk# inputs v in (dc) -0.3 v ddq + 0.3 v input different voltage, clk and clk# inputs v id (dc) -0.36 v ddq + 0.6 v input leakage current i i -5 5 a output leakage current i oz -5 5 a output high voltage v oh v tt + 0.76 - v i oh = -15.2 ma output low voltage v ol v tt ? 0.76 v i ol = +15.2 ma
etrontech 4mx16 ddr sdram em658160 etron confidential 9 rev. 1.1 jan. 2002 capacitance (v dd = 3.3v, f = 1mhz, ta = 25 c) symbol parameter min. max. unit c in input capacitance (except for ck pin) 2.5 5 pf input capacitance (ck pin) 2.5 4 pf c i/o dq, dqs, dm capacitance 4 6.5 pf note: these parameters are periodically sampled and are not 100% tested. recommended d.c. operating conditions (v dd = 3.3v 0.3, ta = 0~70 c) max. parameter symbol - 3.3/3.5/4/5/6/7/8 unit operation current (one bank active) i dd0 t rc = min, t ck = min active-precharge 250/240/230/220/190/180/160 operation current (one bank active) i dd1 burst = 2, t rc = min, cl = 3 i out = 0ma, active-read-precharge 320/300/260/250/220/210/200 precharge power- down standby current i dd2p cke v il (max), t ck = min, all banks idle 80/80/80/65/65/60/55 idel standby current i dd2n cke v ih (min), cs# v ih (min), t ck = min 170/160/150/130/110/100/90 active power-down standby current i dd3p all banks act, cke v il (max), t ck = min 80/80/80/65/65/60/55 active standby current i dd3n one bank; active-precharge, t rc = t ras( max), t ck = min 180/170/160/155/145/140/135 ma operation current (read) i dd4r burst = 2, cl = 3, t ck = min, i out = 0ma 330/310/270/250/220/200/180 operation current (write) i dd4w burst = 2, cl = 3, t ck = min 330/310/270/250/220/200/180 auto refresh current i dd5 t rc( min) 190/180/170/155/145/140/135 self refresh current i dd6 cke 0.2v 2
etrontech 4mx16 ddr sdram em658160 etron confidential 10 rev. 1.1 jan. 2002 electrical characteristics and recommended a.c. operating conditions (v dd = 3.3 0.3 v, ta = 0~70 c) - 3.3/3.5/4/5/6/7/8 symbol parameter min. max. unit t rc row cycle time 44/44/44/55/60/70/80 ns t rfc refresh row cycle time 56/56/56/70/84/91/96 ns t ras row active time 32/32/32/40/42/49/56 120000 ns t rcd /ras to /cas delay 12/12/12/15/18/21/24 ns t rp row precharge time 12/12/12/15/18/21/24 ns t rrd row active to row active delay 6.6/7/8/10/12/14/16 ns tw r write recovery time 2t ck t cdlr last data in to read command 2.5t ck- t dqss t ck t ccd col. address to col. address delay 1t ck t ck clock cycle time cl*=3 3.3/3.5/4/5/6/7/8 15 cl*=2.5 5/5/5.5/6/7.5/8/9 15 cl*=2 6/6/7/8/9/10/11 15 ns t ch clock high level width 0.45 0.55 t ck t cl clock low level width 0.45 0.55 t ck t dqsck dqs-out access time from ck,/ck -0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 0.6/0.6/0.6/0.7/0.7/0.75/0.8 ns t ac output access time from ck,/ck -0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 0.6/0.6/0.6/0.7/0.7/0.75/0.8 ns t dqsq dqs-dq skew -0.5/-0.5/-0.5/-0.5/-0.5/-0.5/-0.6 0.5/0.5/0.5/0.5/0.5/0.5/0.6 ns t rpre read preamble 0.9 1.1 t ck t rpst read postamble 0.4 0.6 t ck t dqss ck to valid dqs-in 0.75 1.25 t ck t wpres dqs-in setup time 0.4/0.4/0.4/0.4/0.45/0.5/0.55 ns t wpreh dqs-in hold time 0.4/0.4/0.4/0.4/0.45/0.5/0.55 ns t wpst dqs write postamble 0.4 0.6 t ck t dqsh dqs in high level pulse width 0.4 0.6 t ck t dqsl dqs in low level pulse width 0.4 0.6 t ck t is address and control input setup time 1.1 ns t ih address and control input hold time 1.1 ns t mrd mode register set cycle time 1t ck t ds dq & dm setup time to dqs 0.4/0.4/0.4/0.4/0.45/0.5/0.55 ns t dh dq & dm hold time to dqs 0.4/0.4/0.4/0.4/0.45/0.5/0.55 ns t qh output dqs valid window 0.3 t ck t pdex power down exit time t is +1t ck t is +2t ck ns t xsa self refresh exit to active command delay 12/12/11/11/10/10/10 t ck t xsr self refresh exit to read command delay 200 t ck
etrontech 4mx16 ddr sdram em658160 etron confidential 11 rev. 1.1 jan. 2002 note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 4. power-up sequence is described in note 6. 5. a.c. test conditions sstl_2 interface reference level of output signals (v rfe ) 0.5 * v ddq output load reference to the under output load (a) input signal levels v ref +0.35 v / v ref -0.35 v input signals slew rate 1 v/ns reference level of input signals 0.5 * v ddq 25 ? output 30pf 25 ? 0.5*v ddq sstl_2 a.c. test load 6. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held "nop" state and maintain cke ? low ? . power applied to v ddq the same time as v tt and v ref. 2) after power-up, no-operation of 200 ? seconds minimum is required. 3) start clock and keep cke ? high ? to maintain either no-operation or device deselect at the input. 4) issue emrs ? enable dll. 5) issue mrs ? reset dll and set device to idle with bit a8 (an additional 200 cycles min of clock are needed for dll lock) 6) precharge all banks of the device. 7) two or more auto refresh commands. 8) issue mrs ? initialize device operation.
etrontech 4mx16 ddr sdram em658160 etron confidential 12 rev. 1.1 jan. 2002 timing waveforms figure 1. ac parameters for read timing (burst length=4, cas latency=2.5) ck cmd dq t ch t ac /ck rea d addr /cs dqs t rpre t dqsq postamble preamble t rpst d0 t cl t ck t ih t is t ih t is d1 d2 d3
etrontech 4mx16 ddr sdram em658160 etron confidential 13 rev. 1.1 jan. 2002 figure 2. ac parameters for write timing (burst length=4) ck cmd dq /ck write addr /cs dqs postamble preamble t wpres t dqss t dsh t wpst t dsl d0 d1 d2 d3 t ds t dh
etrontech 4mx16 ddr sdram em658160 etron confidential 14 rev. 1.1 jan. 2002 figure 3. read command to output data latency (burst length=2) ck cmd dq /ck dqs postamble preamble da0 dq da0 preamble postamble dqs dq da0 preamble postamble dqs cl=2 cl=2.5 cl=3 read da1 da1 da1
etrontech 4mx16 ddr sdram em658160 etron confidential 15 rev. 1.1 jan. 2002 figure 4. read followed by write (burst lenth=4, cas latency=3) ck cmd dq /ck activate addr /cs dqs postamble preamble write row/bank0 col/bank0 d2 d1 t rcdr act rol/bank1 t rrd d0 d3 rea d col/bank0
etrontech 4mx16 ddr sdram em658160 etron confidential 16 rev. 1.1 jan. 2002 figure 5. write followed by read (burst lenth=4, cas latency=3) ck cmd /ck write dq d0 d1 d3 d2 read dqs col col addr /cs d0 d1 t wtr d2 d3
etrontech 4mx16 ddr sdram em658160 etron confidential 17 rev. 1.1 jan. 2002 figure 6. precharge termination of a burst read (burst length=4, cas latency=3) ck cmd /ck read addr /cs dqs postamble preamble precharge col bank bank dq d0 d1 t rp act
etrontech 4mx16 ddr sdram em658160 etron confidential 18 rev. 1.1 jan. 2002 figure 7. precharge termination of a burst write (burst length=4) ck cmd dq /ck activate addr /cs dqs postamble preamble d0 write precharge activate row/bank col/bank row/bank row/bank dqm d1 t rcd t wr t rp t rc t ras t ds t qdh masked by dqm
etrontech 4mx16 ddr sdram em658160 etron confidential 19 rev. 1.1 jan. 2002 figure 8. auto precharge after read burst (cas latency=3) ck cmd dq /ck d0 d1 reada cmd dq d0 d1 reada auto precharge cmd dq reada auto precharge d3 d2 d0 d1 d3 d2 d4 d5 d7 d6 act act act t rp bl=2 bl=4 bl=8 t rp t rp auto precharge
etrontech 4mx16 ddr sdram em658160 etron confidential 20 rev. 1.1 jan. 2002 figure 9. auto precharge after write burst ck cmd dq /ck d0 d1 writea auto precharge cmd dq d0 d1 auto precharge cmd dq auto precharge d3 d2 d0 d1 d3 d2 d4 d5 d7 d6 act act act bl=2 bl=4 bl=8 t rp t wr writea writea dqs postamble preamble dqs postamble preamble dqs postamble preamble t rp t wr t rp t wr
etrontech 4mx16 ddr sdram em658160 etron confidential 21 rev. 1.1 jan. 2002 figure 10. read terminated by burst stop (burst length=8) ck /ck /cs addr cmd bs t d0 d3 d2 d1 dq dqs cl=3 rea d col
etrontech 4mx16 ddr sdram em658160 etron confidential 22 rev. 1.1 jan. 2002 figure 11. read terminated by read (burst length=4, cas latency=3) ck /ck cmd dq addr /cs da0 dqs db3 db2 db1 db0 da1 t ccd read rea d col a col b
etrontech 4mx16 ddr sdram em658160 etron confidential 23 rev. 1.1 jan. 2002 figure 12. mode register set command ck /ck /cs addr cmd precharge mrs data t rp 1 clk mrs act row
etrontech 4mx16 ddr sdram em658160 etron confidential 24 rev. 1.1 jan. 2002 figure 13. active / precharge power down mode ck cke cmd activate / precharge note 1,2 /ck t is t pdex any comman d note: 1. all banks should be in idle state prior to entering precharge power down mode. 2. one of the banks should be in active state prior to entering active power down mode.
etrontech 4mx16 ddr sdram em658160 etron confidential 25 rev. 1.1 jan. 2002 figure 14. self refresh entry and exit cycle ck cmd /ck self refresh enter cke t rc self refresh exit t is auto refresh nop t rc is required before any command can be applied, and 200 cycles of clk are required before a read command can be applied.
etrontech 4mx16 ddr sdram em658160 etron confidential 26 rev. 1.1 jan. 2002 66 pin tsop ii package outline drawing information units: mm 0. 25 typ 0 ~ 8 0.125 + 0.085 - 0.005 0.8 typ 0.5 0.1 33 34 1 66 0. 71 typ 10.16 0.13 22.22 0.13 11.76 0.20 0.30 0.08 0. 65 typ 1.00 0.10 1.20 max 0. 10 max 0.05 min

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